Distinguished Engineer, Test Engineering - DFT Operations Interface and IP Test Methodology

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

To address the multi-trillion-dollar opportunity promised by generative AI, cloud hyperscalers are investing hundreds of billions into AI infrastructure. This makes the AI cloud the latest and fastest-growing addition to a data-center universe that includes on-premises, high-performance computing, and general-purpose cloud computing.

What You Can Expect

Marvell is seeking a seasoned technical leader with deep test engineering background and a strong collaboration skillset to drive the test methodology roadmap for our Accelerated Infrastructure product lines. This position will be responsible for leading our Operations DFT interface, consolidating and optimizing our IP test methodology, and working with DFT and Design Engineering teams to drive testability roadmap. This individual will work with Product/Test Engineering and Design leads across products to drive consistent and high quality test planning.

Key Responsibilities:

• Drive pre-silicon test planning discussion across product lines

• Consolidate IP test methodology across products.

• Work with Design Engineering to ensure IP testability for high-performance analog, high-speed connectivity

• Align structural test roadmap with Operations and DFT

The ideal candidate will bring a strong blend of technical and interpersonal skills that will enable strong collaboration across Operations, DFT, and Design teams to ensure Marvell's test IP portfolio is aligned with its cutting edge product roadmap.

What We're Looking For

• 15+ years test engineering experience. BS in Electrical Engineering (MSEE preferred).

• Technical familiarity with Accelerated Infrastructure Silicon building blocks: Advanced process node (TSMC 5nm and lower geometry), high-density compute, high-speed interface, die to die interface, HBM, Multi-Chip Module

• High-speed test challenges and techniques for copper and electro-optics interfaces

• Knowledge of Advantest, Teradyne platform capabilities

• Test Plan Generation

• Management and Cross-functional leadership

Expected Base Pay Range (USD)

178,600 - 264,290, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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