Staff ATE Test Engineer
Chelsea Search Group
Full-time
On-site
Los Angeles, California, United States
Test Engineer
Staff or Principal Test Engineer
Location: Irvine, CA
Key Responsibilities:
Technical Ownership:
β’ Own test engineering solutions across all product phases: silicon bring-up, characterization, customer sampling, qualification, and high-volume manufacturing.
Test Architecture & Strategy:
β’ Define test strategy, coverage goals, and manufacturing methodologies; develop comprehensive product Test Plans and drive DFT alignment.
ATE Solution Leadership:
Lead all aspects of the test solution including:
β’ Test programs and automation
β’ ATE hardware platforms
β’ Probe cards, load boards, fixturing, and mechanical interfaces
Cross-Functional Leadership:
β’ Act as a core team member for new product introduction, participating in architecture reviews, testability/DFT reviews, and quality trade-off decisions.
Coverage & Optimization:
β’ Partner with Design Engineering to ensure high test coverage, yield optimization, and test time targets.
Correlation & Characterization:
β’ Correlate ATE results with bench validation data; characterize device performance and margins for volume production.
Manufacturing Readiness:
β’ Coordinate with internal manufacturing, technology partners, and sub-cons to drive NPI test release and volume ramp.
Mentorship & Influence:
β’ Provide technical guidance to other test engineers and help shape long-term test infrastructure and standards.
Required Qualifications:
β’ Bachelorβs degree in electrical engineering or related field with 10+ years of test engineering experience (Masterβs preferred).
β’ Expert-level experience with Advantest 93K and/or Teradyne Uflex platforms.
β’ Strong background in mixed-signal ATE development for complex SoCs including:
- High-speed ADC/DAC
- SERDES
- DSP-based devices
β’ Solid understanding of Scan, MBIST, and loop-back test methodologies.
Preferred Qualifications:
β’ Familiarity with bench instrumentation such as Network Analyzers and Sampling Oscilloscopes.
β’ At-speed wafer probe experience.
β’ Experience with schematic capture, PCB layout, and 2D/3D CAD tools.
Location: Irvine, CA
Key Responsibilities:
Technical Ownership:
β’ Own test engineering solutions across all product phases: silicon bring-up, characterization, customer sampling, qualification, and high-volume manufacturing.
Test Architecture & Strategy:
β’ Define test strategy, coverage goals, and manufacturing methodologies; develop comprehensive product Test Plans and drive DFT alignment.
ATE Solution Leadership:
Lead all aspects of the test solution including:
β’ Test programs and automation
β’ ATE hardware platforms
β’ Probe cards, load boards, fixturing, and mechanical interfaces
Cross-Functional Leadership:
β’ Act as a core team member for new product introduction, participating in architecture reviews, testability/DFT reviews, and quality trade-off decisions.
Coverage & Optimization:
β’ Partner with Design Engineering to ensure high test coverage, yield optimization, and test time targets.
Correlation & Characterization:
β’ Correlate ATE results with bench validation data; characterize device performance and margins for volume production.
Manufacturing Readiness:
β’ Coordinate with internal manufacturing, technology partners, and sub-cons to drive NPI test release and volume ramp.
Mentorship & Influence:
β’ Provide technical guidance to other test engineers and help shape long-term test infrastructure and standards.
Required Qualifications:
β’ Bachelorβs degree in electrical engineering or related field with 10+ years of test engineering experience (Masterβs preferred).
β’ Expert-level experience with Advantest 93K and/or Teradyne Uflex platforms.
β’ Strong background in mixed-signal ATE development for complex SoCs including:
- High-speed ADC/DAC
- SERDES
- DSP-based devices
β’ Solid understanding of Scan, MBIST, and loop-back test methodologies.
Preferred Qualifications:
β’ Familiarity with bench instrumentation such as Network Analyzers and Sampling Oscilloscopes.
β’ At-speed wafer probe experience.
β’ Experience with schematic capture, PCB layout, and 2D/3D CAD tools.
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Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)
Β
Javier Leon
Talent Acquisition
Chelsea Search Group
619-227-3193 cell
FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)
Β